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[Driver][SYCL] Correcting a sanitizer fail with null pointer #1965

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Signed-off-by: Harini Chilamantula [email protected]

@@ -4791,6 +4791,9 @@ void Driver::BuildActions(Compilation &C, DerivedArgList &Args,
if (!UnbundlerInputs.empty()) {
Action *PartialLink =
C.MakeAction<PartialLinkJobAction>(UnbundlerInputs, types::TY_Object);
if (!LastArg)
LastArg = &(dyn_cast<InputAction>(UnbundlerInputs.back())->getInputArg());

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Please create a test that exercises the pathway in which we know LastArg will not be set before the partial link occurs.

Naghasan and others added 26 commits June 24, 2020 12:14
SYCL uses a custom mangling scheme (mangles target address space 0).
This patch adds a "binding" layer (sycldevice-binding.cpp).
The binding layer is compiled in sycl device mode which allow to generate
the expected mangling when the target address space is 0.

Signed-off-by: Victor Lomuller <[email protected]>
… category implementation (intel#1958)

The patch moves some include files from libs to include so they can be shared with libspirv side.
Refactor the ptx-nvidiacl side as well and move the following builtins in their own file to avoid symbol redefinition:
- acosh
- asinh
- atanh
- cosh
- erfc

Signed-off-by: Victor Lomuller <[email protected]>
Co-authored-by: David Wood <[email protected]>
The patch changes the type of accessors for USM reductions.
Placeholder accessors were used previously. Regular accessors are used now.

Also, the patch fixes few inaccurate or wrong comment sections.

Signed-off-by: Vyacheslav N Klochkov <[email protected]>
* [SYCL] Fix USM event clearing when calling queue::wait()

Clear the USM events from the queue upon calls to wait() so that they
are not waited for multiple times.

Signed-off-by: Sergey Semenov <[email protected]>
The events were created with the interoperability constructor that
performed an unneeeded retain.

Signed-off-by: Sergey Semenov <[email protected]>
…tation (intel#1943)

This second patch finishes the implementation of SYCL_INTEL_accessor_simplification extension.

It adds:

* `get_host_accessor`  to buffer
* adds overloads for `get_access` to enable deduction guide
* refactored test, as requested in this PR: intel#1838
* updated deduction guides, based on limitations found via refactored tests
Some SYCL unit tests link statically with the Runtime. -nolibsycl option
allows skipping linkage with the default runtime library.

Signed-off-by: Alexander Batashev <[email protected]>
Co-authored-by: Artem Gindinson <[email protected]>
…ntel#1968)

Thus making SPIR AS map continuous.
This is a follow up from a discussion from here: https://reviews.llvm.org/D82174

Signed-off-by: Dmitry Sidorov <[email protected]>
Remove old forward declared SPIR-V builtin from the geometric and common categories.
Update the binding file using the header generator.
Add relevant binding test.
Remove XFAIL from related SYCL tests.

Signed-off-by: Victor Lomuller <[email protected]>
Co-authored-by: David Wood <[email protected]>
Previously, the execution mode of CPU subgroup is emulation mode, which means
a subgroup == a workgroup. Since OCL CPU RT has enabled native subgroups by
default, we need to update these sycl subgroup tests.
…el#1985)

With this extension 2 new Storage Classes are introduced:
DeviceOnlyINTEL and HostOnlyINTEL appropriately mapped on
global_device and global_host SYCL/OpenCL address spaces which
are part of SYCL_INTEL_usm_address_spaces extension.

Co-authored-by: Viktoria Maksimova <[email protected]>

Signed-off-by: Dmitry Sidorov <[email protected]>
Signed-off-by: Viktoria Maksimova <[email protected]>
The issue results in either segfault due to some nullptr dereference or in a deadlock when the buffer gets destroyed and the last access to it was through host task.
Sync the post link process for PTX following the illustration update. Add a description for the global offset handling.

Signed-off-by: Victor Lomuller <[email protected]>
VC intrinsics library is required by LowerESIMD pass.
Features:
- atomic_ref with integral and floating-point specializations
- atomic_fence

Tests:
- exchange
- compare_exchange
- fetch_add, +=, ++
- fetch_sub, -=, --
- fetch_min
- fetch_max

Signed-off-by: John Pennycook <[email protected]>
Co-authored-by: Alexey Sachkov <[email protected]>
Co-authored-by: Roland Schulz <[email protected]>
Make TemplateArgs::getParams() const and return reference instead of
a copy.

Signed-off-by: Konstantin S Bobrovsky <[email protected]>
Create a new extension to enable SPIR-V to use arbitrary precision integers, with a default maximum bitwidth (with this extension) up to 32 bits, but implementers are allowed to go up to any arbitrary bitwidth.
…but FPGA (intel#1986)

Disable SPV_INTEL_usm_storage_classes by default since it adds new
storage classes that represent global_device and global_host address
spaces, which are not supported for all targets. With the extension
disabled the storage classes will be lowered to CrossWorkgroup storage
class that is mapped to just global address space.

The extension is enabled only for FPGA with a flag 'enable-usm-address-spaces'
passed to the driver.

Signed-off-by: Dmitry Sidorov <[email protected]>
…el#1999)

Also, correct select_cl_scalar_integral_xxx type transformation naming typo.

Signed-off-by: Dmitri Mokhov <[email protected]>
If profiling is not explicitly enabled on SYCL events there is no reason to enable timing on the underlying CUDA events. This PR disables timings for CUDA events where `PI_QUEUE_PROFILING_ENABLE` isn't given at creation.

Signed-off-by: Steffen Larsen <[email protected]>
This API returns the backend associated with a platform.
A LIT test has also been added.

Signed-off-by: Gail Lyons <[email protected]>
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something went wrong in my update

againull pushed a commit to againull/llvm that referenced this pull request May 4, 2023
It can only be FlagUnknownPhysicalLayout. There is no way we can
generate it LLVM environment and get use of it, hence the patch just
ignores it if it come from another SPIR-V generator.

In general, there are following possible debug flags for DIBasicType:
BigEndian, LittleEndian and Artificial. There is not way that clang will
ever generate them, but that can be produced by manually writing
assembly and transforming it to LLVM IR. While it can be potential
improvement for the future - I don't see it useful to add to the spec
and implementation right now.

Signed-off-by: Sidorov, Dmitry <[email protected]>

Original commit:
KhronosGroup/SPIRV-LLVM-Translator@d43a4e8
jsji pushed a commit that referenced this pull request Jun 8, 2023
Flags operand is not optional, fill it with DebugInfoNone value (see #1965
for clarifications why it could not be generated by clang or by LLVM
environment).

Original commit:
KhronosGroup/SPIRV-LLVM-Translator@7a54cde
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